3.3v sdram buffer for mobile pcs with four so-dimms CY2310BNZ cypress semiconductor corporation ? 3901 north first street san jose , ca 95134 408-943-2600 document #: 38-07260 rev. *a revised january 28, 2003 features ? one input to 10 output buffer/driver supports up to four sdram so-dimms two additional outputs for feedback smbus interface for output control low skew outputs up to 100 mhz operation multiple v dd and v ss pins for noise reduction dedicated oe pin for testing space-saving 28-pin ssop package 3.3v operation description the CY2310BNZ is a 3.3v buffer designed to distribute high-speed clocks in mobile pc applications. the part has ten outputs, eight of which can be used to drive up to four sdram so-dimms, and the remaining can be used for external feedback to a pll. the device operates at 3.3v and outputs can run up to 100 mhz, thus making it compatible with pentium ii ? processors. the CY2310BNZ can be used in conjunction with the cy2281 or similar clock synthesizer for a full pentium ii motherboard solution. the CY2310BNZ also includes an smbus interface that can enable or disable each output clock. on power-up, all output clocks are enabled. a separate output enable pin facilitates testing on ate. block diagram smbus buf_in sdata sclock sdram0 sdram1 sdram2 sdram3 sdram4 sdram5 sdram6 sdram7 1 2 3 4 v dd sdram7 sdram6 v ss v dd sdram5 28-pin ssop top view pin configuration decoding 8 5 6 7 12 9 10 11 13 14 28 27 26 25 21 24 23 22 17 20 19 18 16 15 sdram4 v ss oe v dd sdram9 v ss v ssiic sclock v dd sdram0 sdram1 v ss v dd sdram2 v ss buf_in v dd sdram8 v ss v ddiic sdata sdram3 sdram8 sdram9 oe CY2310BNZ
CY2310BNZ document #: 38-07260 rev. *a page 2 of 6 device functionality serial configuration map the serial bits will be read by the clock driver in the following order: byte 0 - bits 7, 6, 5, 4, 3, 2, 1, 0 byte 1 - bits 7, 6, 5, 4, 3, 2, 1, 0 . byte n - bits 7, 6, 5, 4, 3, 2, 1, 0 reserved and unused bits should be programmed to ? 0. ? smbus address for the CY2310BNZ is: pin description pins name description 1, 5, 10, 19, 24, 28 v dd 3.3v digital voltage supply 4, 8, 12, 17, 21, 25 v ss ground 13 v ddiic smbus voltage supply 16 v ssiic ground for smbus 9 buf_in input clock 20 oe output enable, three-states outputs when low. internal pull-up to v dd 14 sdata smbus data input, internal pull-up to v dd 15 sclk smbus clock input, internal pull-up to v dd 2, 3, 6, 7 sdram [0 ? 3] sdram byte 0 clock outputs 22, 23, 26, 27 sdram [4 ? 7] sdram byte 1 clock outputs 11, 18 sdram [8 ? 9] sdram byte 2 clock outputs oe sdram [0 ? 17] 0high-z 1 1 x buf_in a6 a5 a4 a3 a2 a1 a0 r/w 1101001 ---- byte 0:sdram active/inactive register (1 = enable, 0 = disable), default = enabled bit pin # description bit 7 ? initialize to 0 bit 6 ? initialize to 0 bit 5 ? initialize to 0 bit 4 ? initialize to 0 bit 3 7 sdram3 (active/inactive) bit 2 6 sdram2 (active/inactive) bit 1 3 sdram1 (active/inactive) bit 0 2 sdram0 (active/inactive) byte 1: sdram active/inactive register (1 = active, 0 = inactive), default = active bit pin # description bit 7 27 sdram7 (active/inactive) bit 6 26 sdram6 (active/inactive) bit 5 23 sdram5 (active/inactive) bit 4 22 sdram4 (active/inactive) bit 3 ? initialize to 0 bit 2 ? initialize to 0 bit 1 ? initialize to 0 bit 0 ? initialize to 0 byte 2: sdram active/inactive register (1 = active, 0 = inactive), default = active bit pin # description bit 7 18 sdram9 (active/inactive) bit 6 11 sdram8 (active/inactive) bit 5 ? reserved, drive to 0 bit 4 ? reserved, drive to 0 bit 3 ? reserved, drive to 0 bit 2 ? reserved, drive to 0 bit 1 ? reserved, drive to 0 bit 0 ? reserved, drive to 0
CY2310BNZ document #: 38-07260 rev. *a page 3 of 6 absolute maximum conditions parameter description condition min. max. unit v dd core supply voltage ? 0.5 7.0 v v in input voltage relative to v ss ? 0.5 v dd +0.5 vdc t s temperature, storage non functional ? 65 +150 c t a temperature, operating ambient functional ? 40 85 c t j temperature, junction functional 150 c ? jc dissipation, junction to case mil-spec 883e method 1012.1 32.24 c/w ? ja dissipation, junction to ambient jedec (jesd 51) 98.31 c/w esd hbm esd protection (human body model) mil-std-883, method 3015 2000 volts ul ? 94 flammability rating @1/8 in. v ? 0 msl moisture sensitivity level 1 ppm dc electrical specifications parameter description condition min. max. unit v dd supply voltage @3.3v 5% 3.135 3.465 v i dd1 3.3v supply current at 64mhz 100 180 ma i dd2 3.3v supply current at 100 mhz 150 220 ma i dd tristate 3.3v supply current in three-state ? 10 ma logic inputs v il input low voltage v ss ? 0.3 0.8 v v ih input high voltage 2.0 v dd +0.5 v i il1 input leakage current, buf_in ? 5+5a i il2 input leakage current [1] ? 20 +5 a logic outputs (sdram0:9) [2] v ol output low voltage i ol = 1 ma ? 50 mv v oh output high voltage i oh = ? 1 ma 3.1 ? v i ol output low current v ol = 1.5v 70 185 ma i oh output high current v oh = 1.5v 65 160 ma pin capacitance/inductance c in input pin capacitance ? 5pf c out output pin capacitance ? 6pf l in input pin inductance ? 7nh c load input load capacitance 20 30 pf ac electrical specifications parameter description test condition min. max. unit f in input frequency at 64 mhz 0 133 mhz t r output rise edge rate measured from 0.4v to 2.4v 1.5 4.0 v/ns t f output fall edge rate measured from 2.4v to 0.4v 1.5 4.0 v/ns t sr output skew, rising edges 200 ps t sf output skew, falling edges 200 ps t en output enable time 1.0 8.0 ns t dis output disable time 1.0 8.0 ns notes: 1. oe, sdata, and sclock logic pins have a 250-k ? internal pull-up resistor (v dd ? 0.8v). 2. all sdram outputs loaded by 6" transmission lines with 22-pf capacitors on ends.
CY2310BNZ document #: 38-07260 rev. *a page 4 of 6 test circuit application information clock traces must be terminated with either series or parallel termination, as they are normally done. summary surface mount, low-esr ceramic capacitors should be used for filtering. typically, these capacitors have a value of 0.1 f. in some cases, smaller value capacitors may be required. the value of the series-terminating resistor satisfies the following equation where rtrace is the loaded characteristic impedance of the trace, rout is the output impedance of the buffer (typically 25w), and rseries is the series terminating resistor. rseries > rtrace ? rout footprints must be laid out for optional emi-reducing capac- itors, which should be placed as close to the terminating resistor as is physically possible. typical values of these capacitors range from 4.7 pf to 22 pf. a ferrite bead may be used to isolate the board v dd from the clock generator v dd island. ensure that the ferrite bead t pr rising edge propagation delay 3.0 5.0 ns t pf falling edge propagation delay 3.0 5.0 ns t dc duty cycle measured at 1.5v 50 60 % z o ac output impedance ? ac electrical specifications (continued) parameter description test condition min. max. unit 0.1 f v dd clk out c load outputs gnd figure 1. test circuit sdram sdata sclk buf_in cpuclk pciclk usbclk ref apic vdd vss ct rs rs vdd 3.3v cd 0.1uf this frequency synthesizer is used to generate cpu, pcl,usb, ref and apic clocks cy2281 ssop 28 CY2310BNZ ssop 28 cd = decoupling capacitor ct = optional emi-reducing capacitor rs = series terminating resistors
CY2310BNZ document #: 38-07260 rev. *a page 5 of 6 ? cypress semiconductor corporation, 2003. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. offers greater than 50w impedance at the clock frequency, under loaded dc conditions. please refer to the application note ? layout and termination techniques for cypress clock generators ? for more details. if a ferrite bead is used, a 10 f ? 22 f tantalum bypass capacitor should be placed close to the ferrite bead. this capacitor prevents power supply droop during current surges. package drawing and dimension pentium ii is a registered trademarks of intel corporation. all product and company names mentioned in this document are trademarks of their respective holders. ordering information ordering code package type operating range CY2310BNZpvc ? 1 28-pin ssop commercial, 0 c to 70 c CY2310BNZpvc ? 1t 28-pin ssop ? tape and reel commercial, 0 c to 70 c CY2310BNZpvi ? 1 28-pin ssop industrial, ? 40 c to 85 c CY2310BNZpvi ? 1t 28-pin ssop ? tape and reel industrial, ? 40 c to 85 c 28-lead (5.3 mm) shrunk small outline package o28 51-85079-*c
CY2310BNZ document #: 38-07260 rev. *a page 6 of 6 document history page document title: CY2310BNZ 3.3v 3.3v sdram buffer for mobile pcs with four so-dimms document number: 38-07260 rev. ecn no. issue date orig. of change description of change ** 110525 02/07/02 szv change from spec number: 38-01089 to 38-07260 *a 121577 01/29/03 rgl corrected the ordering information to match the devmaster. changed the max value of the vdd core supply in the absolute maximum conditions table from 4.6v to 7.0v
|
